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Graphics processing units (GPUs) are the powerhouse behind many modern technologies. From gaming to scientific computing, GPUs handle complex calculations quickly. TSMC, the world’s largest chip manufacturer, predicts a massive leap in chip complexity. They envision GPUs with more than 1 trillion transistors in the next decade. This is a staggering increase compared to current high-end chips, which contain billions of transistors.
Currently, GPUs like Nvidia’s Blackwell B200 have made headlines with their 100 billion transistors. Transistors, the tiny switches inside a chip, are crucial for processing data. In recent years, the growth in transistor count has been phenomenal. But as chips get more complex, making them larger is challenging. Certain components, like SRAM bit cells used for quick data storage, haven’t shrunk much in size recently. This limits how much smaller, and consequently more powerful, chips can become.
Chip size is capped by the reticle limit, which is the maximum area a semiconductor manufacturing tool can expose in a single operation. It’s a boundary defined by the size of the mask or reticle used in lithography, the process of etching chip designs onto silicon wafers. Currently, this limit is around 800 square millimeters. Surpassing this size increases production complexity and cost.
To understand the significance of the reticle limit, let’s delve into chip history. The journey of chip evolution began in the 1960s with a few thousand transistors per chip. By the 1970s, the Intel 4004 processor had 2,300 transistors. Fast forward to the 2000s, and we reached the billion-transistor era with chips like Intel’s Itanium 2. Each leap in transistor count was a technological milestone.
Now, due to the reticle limit, we’re shifting from enlarging single chips to integrating multiple smaller chips, or chiplets. This approach isn’t new but has become crucial for further growth. Chiplets are combined using advanced packaging technologies like CoWoS (Chip on Wafer on Substrate) and SoIC (System on Integrated Chips), enhancing performance and functionality.
TSMC champions this multi-chiplet strategy, foreseeing GPUs with 1 trillion transistors. This involves not just placing chiplets side by side but also stacking them vertically. For instance, Nvidia’s Blackwell B200, although a single unit in appearance, consists of two 104 billion transistor dies interconnected on a silicon base. Similarly, AMD’s MI300X superchip boasts 153 billion transistors through a configuration of four compute dies.
Such designs are predecessors to the trillion-transistor future. But there’s more to it than just piling up transistors. The heat generated by these densely packed circuits poses a significant challenge. Efficient heat management is crucial, especially in 3D stacking, where layers of active silicon are piled up.
TSMC is optimistic about overcoming these hurdles, projecting a tenfold increase in interconnect density. This would not only support the growth in transistor count but also revolutionize chip architectures. With advancements in chiplet integration and 3D stacking, the next generation of chips will be vastly more powerful, marking a new era in semiconductor technology.
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